Phase-locked loops have found many applications in various data and signal processing devices. As examples, phase-locked loops are typically used in transmitters and receivers, signal generators, frequency synthesizers, function generators, etc.
One of the more widely used versions of the phase-locked loop is the divide-by-N phase-locked loop. The divide-by-N phase-locked loop includes a divider circuit to divide the frequency of the output from the phase-locked loop by a selectable constant N. The divided output signal is provided to the input of the phase-locked loop as feedback to be combined in a phase detector with a reference signal having a substantially constant frequency. The output from the phase detector is low-pass filtered and voltage amplified to provide a substantially direct current control signal wherein the voltage magnitude of the control signal is indicative of the phase difference between the feedback signal and the reference signal. The control signal is provided to a voltage-controlled oscillator so that the frequency of the oscillator output is proportional to the magnitude of voltage of the control signal.
The phase-locked loop operates to maintain the frequency of the feedback signal equal to the frequency of the reference signal. Since the frequency of the output signal from the phase-locked loop is divided by N to obtain the feedback signal, the frequency f.sub.o of the output signal is N times the frequency f.sub.r of the reference signal, i.e.: EQU f.sub.o =Nf.sub.r
The frequency of the output signal may be selected by selecting a proper value of the selectable constant N provided to the divider circuit.
Divide-by-N phase-locked loops suffer from several known disadvantages. One of these disadvantages is phase noise that is present on the output signal. The phase noise that is present on the output signal from the divide-by-N phase-locked loop is due in large measure to phase noise introduced by the divider circuit. The divider circuit introduces phase noise that is typically across the frequency spectrum. Therefore, that portion of the divider circuit phase noise inside the loop bandwidth is not substantially filtered by the action of the phase-locked loop and low-pass filter. Accordingly, this noise is transmitted to the output signal and reduces the signal-to-noise ratio thereof.
Further, it has been noted that the phase noise introduced by the divide-by-N counter is a function of the value of the selectable constant N. In other words, the higher the value of the selectable constant N, the greater the phase noise that is introduced by the divider circuit and transmitted to the output signal. A phase-locked loop having an output signal with a wide frequency range requires a divider circuit with a large value of N and, accordingly, the amount of phase noise is increased.
Conventional methods for reducing phase noise and thereby for improving the signal-to-noise ratio of a divide-by-N phase-locked loop include reducing the loop bandwidth so that the filter and other components of the phase-locked loop naturally filter a greater portion of the phase noise. However, reducing the loop bandwidth decreases the switching speed of the phase-locked loop and, therefore, is an undesirable construction. Further, as mentioned above, phase noise introduced by the divider circuit typically appears across the entire frequency spectrum and is, therefore, impossible to completely filter by reducing the loop bandwidth.
Accordingly, it is desirable to provide a phase-locked loop wherein the phase noise introduced by the divide-by-N divider circuit can be substantially attenuated without unnecessary restriction on the bandwidth or switching speed of the phase-locked loop.